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Below are the top discussions from Reddit that mention this online Coursera course from University of Illinois at Urbana-Champaign.

You should complete the VLSI CAD Part I: Logic course before beginning this course.

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Taught by
Rob A. Rutenbar
Adjunct Professor
and 11 more instructors

Offered by
University of Illinois at Urbana-Champaign

Reddit Posts and Comments

0 posts • 1 mentions • top 1 shown below

r/vlsi • comment
2 points • flym4n

> the design eng: do they ever partition the design in blocks first (perhaps on paper), or do they just start writing code?

Yes! There's more than one design engineer. We start with pen and paper (well, mostly digital pen and paper). Even inside the blocks, you first draw the rough layout of what communicates with what, then you get to coding, modify the paper drawing if you forgot about something, etc. It's iterative.

> Also, am I correct in thinking they don't really look below the gate level? > Can you really basically forget about the implementation technology as a design eng, and just work with RTL and gates?

Yes. You think about the technology in an abstract manner. For example, "should I duplicate this decoding logic in the two pipeline stages to avoid one register?" or "how do I limit the fan-in/fan-out of this piece of logic". You're not thinking about the individual voltages and RC constants.

> the verification eng: do they only verify functional requirements (basically assertions on binary in and out)? If that's the case, who verifies non-functional requirements like timing, power, etc.?

Functional only. Timing and power is checked by the implementation people.

> in case they want / need to modify the design, do they do it themselves, or do they ask the design eng?

They would ask the designer, since s/he knows best what the design is doing, and what the modification would require

> Also, any pros and cons in being a design eng, as opposed to the other roles?

It's mostly a matter of taste (and job availability). You need a bit of a longer training to be useful as an implementation engineer, as each tool is different, while writing RTL is still writing RTL whether you're using cadence or synopsys.

They all have their pros and cons: with design you're making the real end-product, and you're the person that will make or break the PPA.

Failed verification destroys a product, or even a company (we're still talking about the FDIV bug, and it happened in '94). Verification is closer to software engineering, you're not really thinking about anything physical.

Edit: This course is great if you want to understand the basics of an implementation tool: https://www.coursera.org/learn/vlsi-cad-layout/